Eye diagrams are a conventional format for representing parametric information about signals, and especially digital signals. We shall refer to an item of test equipment or a measurement circuit arrangement that creates an eye diagram as an eye diagram tester, whether it is found in an oscilloscope, a BERT (Bit Error Rate Tester), or, as we shall show how, in a logic analyzer. ""Scopes and BERTs each have their own types of circuit architecture that they use to measure eye diagrams, and thus belong to the class of Eye Diagram Testers. The method and circuit apparatus to be disclosed herein is different than that used in ""scopes and BERTs, and is especially suitable for use within a logic analyzer. We shall call this different method and circuit apparatus an Eye Diagram Analyzer, or EDA for short. By the definitions above, an EDA is a particular type of eye diagram tester.
Although the method and apparatus for an EDA to be described herein is especially suitable for use within the architecture of a logic analyzer, it will be readily appreciated that it could also be used to create a stand-alone eye diagram analyzer (and at a considerable savings in hardware, such as the large acquisition memory, otherwise needed to implement a functioning logic analyzer).
To look ahead briefly, an example eye diagram for a digital signal and composed of traces 3 and 4 is illustrated as part of FIG. 1. It is a composite of many (probably at least thousands, easily millions, and perhaps orders of magnitude more) measurements taken upon separate instances of a signal occurring on a channel of interest. To borrow an idea from the world of oscilloscopes, it is as though an infinite persistence continuous time domain trace were cut apart into lengths corresponding to one, five or ten clock times, and then stacked on top of each other. The vertical axis is voltage, and the horizontal axis represents the difference in time (i.e., an offset) between some reference event 2 and an event of interest. The time axis in the example of FIG. 1 has enough length to depict one complete eye centered about the reference 2, with perhaps an additional one half an eye before and after. In general, the number of cycles shown depends upon how the measurement is set up, and could be a large number. In this diagram the reference 2 represents the expected point in time when the value of an applied data signal would be captured by some receiving circuit in an SUT (System Under Test), and is derived from an application of the SUT""s clock to the Eye Diagram Analyzer.
The traces 3 and 4 are the substance of the eye diagram, and represent various combinations of circumstances that occurred in the data signal being characterized (which data signal is also applied to the EDA). For example, consider the circular region 5 about trace 4. That region loosely represents the combination of a specified voltage at such and such a time relative to the SUT""s clock signal, and which might suggest to us that a signal of interest is achieving a proper voltage at a proper time. In our example the trace 4 does indeed transit the circle 5 (note that the circle is merely an annotation or legend within the figure, and not part of any actual eye diagram), which indicates that there actually were times when the data signal had fully (or almost) transitioned at the time indicated relative to when the clock signal finished its transition from one value to the other (which in this case is about a half-cycle ahead of the clock). We also note that another region, say 8, is not transited by the trace, which if that were indeed to happen, would presumably be an indication of trouble. Thickening of the traces 3 and 4 are indicative of jitter, and illuminated pixels detached from the trace, or, line segments that go through the otherwise empty middle of the eye, are generally indications of unfavorable conditions. An eye diagram cannot reveal which isolated instance of the signal caused an exception, as other types of measurements might, but it does provide timely valid information about how a system is operating.
Although eye diagrams go back a long way and were originally made with analog ""scopes, such ""scopes are just not up to the task of performing that function with today""s high speed digital signals, and need not be further considered. Digital oscilloscopes are presently often used to generate eye diagrams.
Digital oscilloscopes operate in various ways with regard to when they decide to sample an input voltage and then measure the voltage at the time of the sample (high speed sequential sampling of solitary events, regular repetitive sampling of periodic signals, random repetitive sampling, etc.) In whatever way it is done, the result is many individual points expressed as pairs of numbers (time, voltage) that must be stored in some sort of acquisition memory and then later interpreted to produce an eye diagram.
BERTs have also been used to generate eye diagrams. A BERT does not have the digitizing ability of the digital oscilloscope. It can determine whether an input signal and a known good reference signal have each crossed a threshold VT at various times along a sweep for a delayed clock, and if the resulting logical values are in agreement or not. The value for VT is also swept. They thus accumulate numbers of data errors on single points that are transitions of VT at swept points in time, which can then be interpreted to create an eye diagram.
Logic Analyzers have heretofore not been capable of generating eye diagrams, as the internal architecture of a conventional logic analyzer does not immediately lend itself to that task. As the popularity of eye diagrams increases, however, it has become increasingly desirable that logic analyzers be equipped to perform this task. The question becomes how to do so economically and take maximum advantage of the resources already present for logic analysis purposes. It would also be desirable if there were a low cost technique for implementing a stand-alone eye diagram analyzer. What to do?
A logic analyzer can be equipped to perform eye diagram measurements by equipping each SUT clock signal input and each SUT data signal input channel with individually variable delays in their respective signal paths. If the range of signal delay is, say, n-many SUT clock cycles, then the SUT clock signal delay might be set at about n/2. For each data channel that is to undergo eye diagram measurement, there is specified some combination of a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold) is essentially a location on an eye diagram, although the trace may or may not ever go through that location. There is also specified how many times this specified combination will be watched before another such combination is invoked. As the SUT runs, a particular specified combination will occur always, sometimes or never. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (hereinafter called xe2x80x9chitsxe2x80x9d). After watching a specified combination for the requisite length of time or number of events, the number of SUT clock cycles involved and the associated number of hits are stored in memory using a data structure indexed by the components of the specified combination (data signal delay, threshold and which channel). Next, a new combination of data signal delay and threshold is specified and a measurement taken and recorded in the data structure. The process is repeated until all possible combinations within a stated range of data signal delay and threshold voltage (using specified resolution/step sizes for delay and voltage) have been investigated. The range of data signal delay might be as large as from zero to n-many SUT clock cycles (which would be n/2 before and after the delayed reference), or it could be some lesser amount. As this process proceeds under the control of firmware within the logic analyzer, other firmware can be examining the data structure and generating a partial eye diagram visible on a display, and that will be complete soon after the measurement itself is finished. This technique can also be used to implement a stand alone eye diagram analyzer.